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This position is an excellent opportunity for an expert RTL design engineer to join a creative, multi-disciplinary, multi-cultural team developing IP that is essential to technology platforms across the industry!
This role is within the System Memory Management Unit (SMMU) team. As part of the continued expansion of the SMMU team into new business areas such as automotive, we are looking to hire passionate RTL design and verification engineers in the Bristol office. If you have experience or interest in automotive IP development, this is an exciting opportunity to join a growing team.
The SMMU is a key component of the Arm Architecture and implements one of the most significant algorithms in modern computing systems: address translation and memory protection. The SMMU team is developing next-generation Arm SMMU implementations targeting high-end mobile, networking, and enterprise markets.
The team employs the latest hardware design and verification methodologies to develop sophisticated, performance efficient and highly configurable hardware IP, enabling delivery to multiple partners with diverse requirements.
As an RTL Design Engineer, you would be required to:
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Analyse proposed specifications to understand implementation challenges and opportunities, working with the architects to improve and refine the ideas
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Plan, track and coordinate tasks for yourself and your team
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Work with modelling, verification, performance analysis and back-end implementation colleagues to ensure your design meets all the functional and performance requirements
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Improve design methodology to meet evolving needs
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Lead and mentor other team members as they learn and solve new problems.
You will be responsible for development of one or more functional blocks of the IP. Possess an in-depth understanding of all the aspects of the products’ successful delivery, including low-power design techniques, awareness of the impact of design decisions on system performance, ability to produce designs that are area efficient, and the verification techniques that are employed to ensure high-quality, innovative designs
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Demonstration of a strong delivery record of high quality, low power, high performance sophisticated micro-architecture and RTL design using System Verilog, Verilog or VHDL in reasonable timescales.
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Be able to navigate and make high-level design trade-offs and articulate the rationale for those choices.
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Knowledgeable on ASIC (or FPGA) design methodology, IP signoff methods with a deep understanding on timing/area/complexity trade-offs for complex data path designs.
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Team leadership and mentoring experience
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Knowledge of memory system interconnect protocols (e.g. AMBA ACE-Lite or AXI)
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Solid understanding of SystemVerilog Assertions (SVA) and formal verification
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Experience of a scripting language such as Perl, Tcl, C shell, Pytho
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Knowledge of a number hardware verification languages e.g. SystemVerilog
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You have already worked on Functional Safety product development for the Automotive market (applying standards such as ISO 26262 and/or IEC 61508)
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Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of any characteristic.
Arm’s hybrid approach to working is centred around flexibility, where we split our time between the office and other locations to get our work done. We empower groups/teams to determine their hybrid working pattern, with an expected minimum attendance in the office of 20% per month, depending on the work, level of experience and team’s needs. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution.